1. Field of the Invention
The present invention relates generally to technology for programming non-volatile memory devices.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying appropriate voltages to control gate 120CG for select gate 120. Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG of select gate 122. Each of the transistors 100, 102, 104 and 106 includes a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.
Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors and four memory cells. For example, NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226 and 228. NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248. Each string is connected to the source line by its select transistor (e.g. select transistor 230 and select transistor 250). A selection line SGS is used to control the source side select gates. The various NAND strings are connected to respective bit lines by select transistors 220, 240, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be in common. Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242. Word line WL2 is connected to the control gates for memory cell 224 and memory cell 244. Word line WL1 is connected to the control gates for memory cell 226 and memory cell 246. Word line WL0 is connected to the control gates for memory cell 228 and memory cell 248. As can be seen, each bit line and the respective NAND string comprise the columns of the array of memory cells. The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array. Each word line connects the control gates of each memory cell in the row. For example, word line WL2 is connected to the control gates for memory cells 224, 244 and 252.
Each memory cell can store data (analog or digital). When storing one bit of digital data, the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data “1” and “0.” In one example of a NAND type flash memory, the voltage threshold is negative after the memory cell is erased, and defined as logic “1.” The threshold voltage after a program operation is positive and defined as logic “0.” When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored. A memory cell can also store multiple levels of information, for example, multiple bits of digital data. In the case of storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information are stored, there will be four threshold voltage ranges assigned to the data values “11”, “10”, “00”, and “01.” In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as “11”. Positive threshold voltages are used for the states of “10”, “00”, and “01.”
Typically, a block or other unit of memory cells is erased prior to programming the memory cells to one or more threshold voltage levels as well as in response to a request to erase a portion of the memory. In one embodiment, a block or sector can refer to a minimum number of memory cells that are simultaneously erased. An entire memory device or one or more blocks can be erased during operation of the device.
Relevant examples of NAND type flash memories and their operation are provided in the following U.S. Patents/Patent Applications, all of which are incorporated herein by reference: U.S. Pat. No. 5,570,315; U.S. Pat. No. 5,774,397, U.S. Pat. No. 6,046,935, U.S. Pat. No. 6,456,528 and U.S. Pat. Application. Ser. No. 09/893,277 (Publication No. U.S. 2003/0002348). Other types of flash memory devices can also be used in accordance with embodiments of the present invention. For example, the following patents describe NOR type flash memories and are incorporated herein by reference in their entirety: U.S. Pat. Nos. 5,095,344; 5,172,338; 5,890,192 and 6,151,248. Another example of a flash memory type is found in U.S. Pat. No. 6,151,248, incorporated herein by reference in its entirety.
During manufacturing, it is possible that some flash memory devices or portions thereof become defective. Individual transistors, strings, or blocks of storage elements may be defective and unusable. Additionally, defects in the device may arise after the manufacturing process or during user operation. Defects can be effectively managed in most situations by using error correction codes (ECC) or simply not using defective portions of the device. Individual cells, strings, or blocks can be mapped to alternate areas of the memory device, such as predesignated alternate strings at the end of a block. If left undetected, however, defects can cause erroneous erase verification and in some cases, irretrievable user data. Accordingly, various techniques are employed to detect and accommodate defects in flash memory devices.
Defects in flash memory can be discovered during programming and erasing of flash memory. Groups of cells having defective storage elements or select gates will not program or erase properly, indicating a problem with one or more of the devices in the string. During manufacturing, defects in flash memory may be discovered during a number of routine testing operations that are performed as part of the manufacturing process. For example, portions of the device may be erased and then verified for an erased condition. Those cells that fail a number of erase attempts may be determined to be defective and handled under one or more defect management schemes.
The manufacturing process also typically includes reading each cell to determine if it is functioning properly. For example, after erasing a group of cells or programming a random pattern to the group, each of the individual cells of the group are individually read. If the state of a cell does not match the value for which it was programmed, it can be determined to be defective.
During user operation, defects can be detected by cells, strings, or blocks that fail to erase or program properly. For example, if a cell fails to erase after a number of attempts, the cell can be determined to be defective. Similarly, if a cell fails to program to a desired state after a number of attempts, it can be determined to be defective. During manufacturing and user operation, erase verification is typically performed by testing a group of cells in a single step.
Although these techniques can discover some defects in a memory device and verify erasure to an extent, they may not fully verify that cells are erased and detect all defects in the device.
Accordingly, there is a need for an improved system and method to verify erase operations and detect defects in non-volatile memory.